High spread highly randomized generatable interleavers

ABSTRACT

Methods and apparatus for generating and performing digital communications using a randomized generatable interleaver. In accordance with one exemplary embodiment of the invention, a pseudo random interleaver of size n*m with excellent randomness and spread properties may be generated from a set of seed values. The interleaver of size N=n*m is defined by dividing the N possible address in the interleaver (0-N−1) into n subsets. The subsets are preferably generatable from a single value within the subset either using an algorithm or a memory based lookup table. The set of n seeds comprises one value selected from each subset. An improved communication system incorporating the aforementioned interleaver and using turbo codes or other concatenated coding systems is also disclosed.

PRIORITY AND CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of co-pending U.S.application Ser. No. 10/285,262 of the same title filed Oct. 30, 2002,which is a divisional of co-pending U.S. application Ser. No. 09/742,248filed Dec. 20, 2000 and entitled “SYSTEM AND METHOD FOR HIGH SPEEDPROCESSING OF TURBO CODES,” which claims priority to provisional U.S.Application Ser. No. 60/174,298 filed Jan. 3, 2000 entitled “ITERATIVEDECODING ARCHITECTURE”, and provisional U.S. Application Ser. No.60/174,290 entitled “SYSTEM AND METHOD FOR EFFICIENT PARALLEL PROCESSINGOF TURBO CODES” filed Jan. 3, 2000, all assigned to the assignee of thepresent invention, all incorporated herein by reference in theirentirety.

FIELD OF THE INVENTION

The present invention is related to the field of digital communications.More particularly, the present invention is a method and apparatus for,inter alia, conducting digital communications using a generatable pseudorandom interleaver.

DESCRIPTION OF RELATED TECHNOLOGY

Turbo coding is a recently developed forward error correction coding anddecoding technique that provides previously unavailable error correctionperformance. A general description of a parallel turbo code can be foundin U.S. Pat. No. 5,446,747 entitled “Error-correction Coding Method Withat Least Two Systematic Convolution Codings in Parallel, CorrespondingIterative Decoding Method, Decoding Module and Decoder,” filed Apr. 16,1992 assigned to France Telecom and incorporated herein by reference.The enhanced level of error correction provided by turbo codesfacilitates the transmission of data over noisy channels, therebyimproving the data transmission capability of all sorts ofcommunications systems.

Some characteristics of turbo codes combine to make the associateddecoders more difficult to implement in an integrated circuit. Thesecharacteristics include large frame sizes, the use of repeated decodingsteps that incorporate extrinsic information, and the use of a pseudorandom interleaver for generating interleaved versions of thetransmitted information and extrinsic information used during encodingand decoding. Additionally, many turbo-coding schemes require asufficiently high degree of randomness in the psuedo random interleaverthat the data sequence must be stored in memory rather than calculatedon the fly.

This combination of characteristics causes turbo codes to require, ingeneral, greater processing resources than other forward errorcorrection coding techniques. For example, the use of repeated decodingsteps increases the decoding time. The (typically) large frame sizecombined with the use of extrinsic information during decoding increasesthe amount of memory required to implement a decoder.

Additionally, the use of a pseudo random interleaver complicates theability to decode a frame in parallel because extrinsic and sampleinformation can not be accessed in an orderly fashion. Memoryrequirements are further increased by the use of memory basedinterleavers, which are preferred when turbo codes having the bestperformance are required. The use of memory based-interleavers can alsoreduce the speed of the decoder since the interleaver typically has tobe accessed twice during a decoding subiteration. This limits thepossible decoding speed to half the memory access rate, which is oftenmuch slower than the rate of other available circuits.

In the paper, S. Crozier, “New High-Spread High-Distance Interleaversfor Turbo Codes”, 20-th biennial Symposium on Communications (Kingston,Canada, May 2000), pp. 3-7, various high spread pseudo randominterleavers are described, including a high-spread random interleaveras well as a “dithered-diagonal” interleaver. These interleavers provideexcellent “spreading” properties while also maintaining sufficientrandomness to provide good performance when incorporated into a turbodecoder.

One interleaver described in the paper is a high spread randominterleaver. The high spread interleaver is generated by randomlygenerating real numbers, applying a spread test, and then rejectingthose numbers that do not pass the spread test. Finally, a sorting stepis performed. The resulting interleaver provides excellent performancewhen used in a turbo code, but cannot be generated in real time on anintegrated circuit due in part to the sorting step. Because theseinterleavers cannot be generated in real time, they typically must bestored in memory consuming large amounts of chip area.

The paper also describes a dithered-diagonal interleaver including anumber of variations. In the most general variation, interleavergeneration requires dithering a set of diagonal lines and then enclosinga block K of these dithered values. The resulting values are sorted todetermine integer read and write indexes.

While the dithered-diagonal interleavers also provide good spreading andrandomness properties, in their most general form, dithered-diagonalinterleavers can not be generated on the fly. Thus, the dithereddiagonal interleaver also requires substantial circuit area for realtime implementation on an integrated circuit.

The above referenced paper does describe one generatable variation ofthe dithered diagonal interleaver, (referred to herein as the“generatable dithered diagonal” (GDD) interleaver). However, in order tomake the interleaver generatable, the GDD interleaver places somerestrictions on the size of the interleaver and the dithering that canbe performed.

These restrictions significantly reduce the performance and usefulnessof this interleaver in a turbo code because the restrictionssignificantly reduce the randomness property of the interleaver. Theperformance reduction worsens as the size the interleaver increases.

Thus, while the paper sets forth many very useful interleavers, it doesnot supply a highly flexible, readily generatable interleaver that hasperformance in a turbo code comparable to the state of the artnon-generatable interleavers.

The types of systems that can benefit from the use of Turbo Codesinclude packet based local area networking (LAN) systems. This isparticularly true where the transmission media is noisy or imperfectincluding RF signal transmitted in the open or via a noisy medium suchas power lines. Thus, it would be useful to have a Turbo Code withpacket sizes that supported typical LAN communications, as well as videoand audio packets.

SUMMARY OF THE INVENTION

The present invention is directed to providing a decoding circuit thatminimizes the negative effect the above described characteristics haveon performance and cost, thereby increasing the number of applicationsfor which turbo codes may be used in a practical and economic manner.Additionally, the present invention is directed to a turbo decoderarchitecture that provides broadband using a practical amount ofcircuitry and memory.

In another aspect of the invention, a method and apparatus forgenerating and performing digital communications using a randomizedgeneratable interleaver is described. In accordance with one embodimentof the invention, a pseudo random interleaver of size n*m with excellentrandomness and spread properties may be generated form set a set of seedvalues.

In one exemplary embodiment, the interleaver of size N=n*m is definedby, dividing the N possible address in the interleaver (0-N−1) into nsubsets. The subsets are preferably generatable from a single valuewithin the subset either using an algorithm or a memory based lookuptable. To select the set of n seeds one value from each subset isselected.

The interleaver is preferably employed in a communication systemincorporating the use of turbo codes or other concatenated codingsystems incorporated the use of pseudo-random interleavers such asserial concatenated codes or hybrids.

Embodiments of the invention that include interleavers of size 2304,2080 and 64 addresses are provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram that illustrates a fundamental operationperformed when doing iterative decoding;

FIG. 2 is a block diagram illustrating an interleaver configured inaccordance with one embodiment ofthe invention;

FIG. 3 is a diagram of a generated interleaver partitioned in accordancewith one embodiment of the invention;

FIG. 4 is diagram illustrating the address placement within the M=4memory banks in accordance with one embodiment of the invention;

FIG. 5 is a block diagram of a portion of a turbo decoder configured inaccordance with one embodiment of the present invention;

FIGS. 6A and 6B show an iterative decoder configured in accordance withan alternative embodiment of the invention in which a non-indexedinterleaver is used.

FIG. 7 is a block diagram of a turbo encoder and decoder configured inaccordance with one embodiment of the invention.

FIG. 8 is a block diagram of a turbo decoder configured in accordancewith one embodiment of the invention.

FIG. 9 is a flow chart illustrating the generation of the interleaveraddresses in accordance with one embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a block diagram that illustrates a fundamental operationperformed when doing iterative decoding. During decoding, receivesamples are processed through add circuits 106 and decoder circuits 100.Decoder circuits are preferably soft-in-soft-out (SISO) decoders such asMAP decoders that perform the maximum a posteriori decoding algorithm.

To speed up processing each decoder 100 processes a portion of the framesimultaneously, or in parallel. The output of the decoders is passed toan interleaver 102 (which could also be a deinterleaver). Interleaver102 reroutes the data to a set of memory banks 104. Once all the data isprocessed a second iteration is performed using the receive samples aswell as the data stored in memory banks 104.

The performance of the above described decoder is adversely impacted bythe use of interleaver 102, however. In particular, the interleavingpattern will often require that the output of two or more decoders to bewritten to the same memory 104. Because the memory can only receive onevalue at any given time, the one decoder must be stalled, or the valuestored, until the memory become available. This delays the speed atwhich decoding can be done, and reduces the benefit of using multipledecoders in parallel. Where such delay can be avoided it would beadvantageous.

A system and method for high efficiency high performance processing ofturbo codes is described. In accordance with one embodiment of theinvention, an interleaver for interleaving code symbols is provided, theinterleaver having a plurality of subsections, each subsection having aset of addresses and each address having an index, wherein asubstantially constant relationship exists from any one subsection toany other subsection between the index of each address at a particularlocation. In a second embodiment of the invention, a forward errorcorrection decoder has a plurality of memory elements, each for storingdata associated with a valid index value, a plurality of decoders, eachfor decoding a subsection from said interleaver, and M interleaversubsections, where said M interleaver subsections each have addressesand said addresses are generated in sets of n values separated by avalue SET_STEP, and wherein each subsection is comprised of r sets of nvalues, where r is an integer multiple of M.

FIG. 2 is a block diagram illustrating an interleaver configured inaccordance with one embodiment of the invention. Address memory 200contains the set of addresses that define the interleaver. Theinterleaver address space is divided into subsections that correspond tothe portions of the frame that will be decoded by a particular decoder.

Hash functions 202 receive the addresses and generate a hash index valuebased on the address. In one embodiment of the invention, the hash indexis used to determine the particular memory to which the data value willbe written. So the number of possible hash index values is preferablythe same as the number of memories 104.

The application of the hash function 202 to each subset of addressproduces an index list (206). In accordance with one embodiment of theinvention, the interleaver addresses are selected such that the indexfor the set of addresses at a particular location with the subset willbe different for each subsection. Thus, as decoding is performed, eachdecoder will be writing to a different memory bank 104, and therefore nomemory contention will take place. This will allow the decoder to takefull advantage of the multiple MAP decoders.

Various alternative address selections can be performed. For example,the addresses can be chosen simply so that the index lists for eachsubsection has a constant relationship between indexes at the samelocation. Writing to the memory banks can then be “pipelined” so thatsubstantially all of the benefit of the multiple decoder can berealized.

In an exemplary embodiment, the hash function can merely select the fourleast significant bits of the address as the hash index. Thus, theaddresses are chosen so that the addresses in a particular locationwithin the subsection have a unique four least significant bits whencompared to the other addresses in the other subsections. An interleaverwith this characteristic can be generated simply by sorting an existinginterleaver based on the index selection criteria.

If values are left over after the sort, they can be inserted at thebeginning of the interleaver and another sort performed. Typically afully indexed interleaver with reasonable randomness can be arrived atafter a reasonable number of sort in this fashion.

It should also be noted that some relative prime interleavers also havecharacteristic of being full indexed.

An alternative hash function is simply to divide the address by the sizeof the subsection. While the division operation is more computationallyintensive, this organizes the memory into one large virtual memory,which facilitates read and writing to the memory during iterations inwhich interleaving is not performed.

In accordance with another embodiment of the invention, a turbo code maybe efficiently decoded using various generated interleavers withexcellent spreading properties. Various embodiments of theseinterleavers are described subsequently herein with respect to FIGS.7-9. These embodiment include, inter alia, interleavers generated byrepeatedly adding an increment amount to an initial set of seed values.These interleavers provide excellent error correction performance withreduced memory requirements, and therefore are highly desirable. Thus,an embodiment of the present invention that incorporates theseinterleavers is highly desirable.

As noted above, many of the interleavers described subsequently hereinare generated by repeatedly adding an increment amount to an initial setof seed values. In various different embodiments, the increment amountis referred to using different terms. For purposes of the followingdescription, the increment amount is referred to as SET_STEP; however,it will be appreciated by those of ordinary skill that the applicabilityof the invention is not limited to those embodiments of the inventionwhich also use the term SET_STEP, the foregoing being merely exemplary.

FIG. 3 is a diagram of a generated interleaver partitioned in accordancewith one embodiment of the invention. The interleaver 300 containsaddresses in locations 0,1,2 . . . N, that are used to permute data forencoding and decoding in a turbo code based forward error correctionsystem. It should be noted, that the numbers 0, 1, 2 . . . N are merelythe locations of the interleaver addresses, and not the interleaveraddresses themselves.

In the described embodiment of the invention, the interleaver 300 isdivided into M=4 subsection 302(a)-(d). An M of 4 is just used forexample. Any alternative number of subsections M may be used. The foursubsection preferably correspond to the number of decoding units(typically SISO decoders) that will be performing the decoding inparallel. Thus, in the described embodiment there are M interleaversubsections and M decoders operating in parallel.

Still referring to FIG. 3, the subsections 302 are further divided intowindows of size n, where n is the number of seeds used to generate theinterleaver. Typically, the first set of values in the interleaver arethe seeds, which is denoted in FIG. 3.

As described in the above referenced patent, the addresses in theinterleaver are then generated by adding a value SET_STEP to the set ofn previous addresses. Thus, the second set of n addresses differ fromthe first set of n addresses by the amount SET_STEP. For example, the(n+1)th address will differ from the 1^(st) address by SET_STEP, and the(n+2)th address will difference from the 2^(nd) address by SET_STEP aswell.

As illustrated, the subsections are comprised of a set of r*n addresses,where n is the size of the seed set, and r is an integer number that isan even multiple of M (where, as described above M, the number ofdecoder units). Alternatively, r can be a integer value that is relativeprime to M.

Since the second subsection 302(b) begins r sets of n addresses afterthe first address, and each set of n addresses is different by SET_STEPfrom the previous set, the difference between first address of the firstsubset, and the first address in the second subset 302(b) is r*SET_STEP.Similarly, the difference between the second address of the firstsubset, and the second address in the second subset 302(b) is alsor*SET_STEP.

This relationship extends between all the subsets 302. In particular,the i^(th) value for any given subset, will be some multiple ofr*SET_STEP from the i^(th) value in another subset 302. Across allsubsets, the i^(th) value in any subset 302 will be some multiple q ofr*SET_STEP, where q is between 1 and (M−1).

This relationship between the i^(th) value of any subset 302 allows anindex for a fully indexed interleaver to be established. Once the indexhas been established, the iterative decoding can be performed in ahighly efficient parallel fashion as described herein.

In particular, by creating an index that is based on r*SET_STEP, it canbe ensured that a fully parallel decoding can be performed with theperformance benefit of the highly spread and generatable interleavers.This enables the implementation of turbo decoders that are high speed,high performance and high efficiency.

In accordance with one embodiment of the invention, the index is theaddress A is integer-divided by r*SET_STEP. A modulo M (% M) operationis then performed on the result, yielding the address index. That is, inone embodiment of the invention the index value is calculated asfollows:Index=trunc(A/r*SET_STEP)% M  (1)

Where A is the address, trunc( ) removes the remainder of the divideoperation, and % is a modulo operation.

In many cases, selecting the proper value for r will not allow theinterleaver to be divided into M equal sized subsections. In oneembodiment of the invention, this is dealt with by making the lastsubsection 302 shorter than the previous subsections (althoughpreferably as close to the same as possible). This will cause onedecoder and memory to not be used for a portion of the decodingsubiteration, but the overall reduction in efficiency will be minimal ifthe shorter subsection is kept close in size to the other subsection,and in all cases the reduction in efficiency will be much less than ifno indexing is used at all.

It should be understood that although this indexing represents a highlyefficient and easy to implement way to take advantage of the regularityof the above described interleavers, other indexing methods for thesetypes of interleavers may be employed in accordance with the invention.In general, the method described with respect to equation (1) is moregeneralized than other indexing methods may be.

For example, for certain size interleavers and certain values ofSET_STEP, r*SET_STEP is equal to the number of bits in the subsection302. In this case, the index may simply be set to the address divided bythe size of the subsection (an embodiment already described above inmore general terms). One example of an interleaver that meet thiscondition is the interleaver where m=2n, and the SET_STEP size is n, andresulting interleaver of size N can be divided evenly into Msubsections.

FIG. 4 is diagram illustrating the address placement within the M=4memory banks in accordance with one embodiment of the invention. Fourextrinsic information memories 400 are shown in accordance with the useof 4 decoders.

Within memory 400, the information is placed according to the associatedaddress. As illustrated, memory 400(a) contains information associatedwith the first r*SET_STEP addresses (from address 1 to addressr*SET_STEP). Memory 400(b) contains information associated with the2^(nd) set of r*SET_STEP addresses, memory 400(c) contains theinformation associated with the 3^(rd) set of r*SET_STEP addresses, andmemory 400(d) contains the information associated with the 4^(th) set ofr*SET_STEP addresses.

More generally, memory 400(a) contains the information associated with(1+4p)r*SET_STEP sets of addresses, memory 400(b) contains theinformation associated with (2+4p)r*SET_STEP sets of addresses, memory400(c) contains the information associated with (3+4p)r*SET_STEP sets ofaddresses, and memory 400(d) contains the information associated with(4+4p)r*SET_STEP sets of addresses, where p goes from 0 to the last setof r*SET_STEP of addresses within N.

More generally still, each memory contains addresses associated with aparticular index value.

As should be apparent, by storing the information as shown in FIG. 4,the information necessary for the next decoding step performed by the Mdecoders will all be located in different memory banks since the i^(th)value across all subsections will be separated from one another by theamount r*SET_STEP. Thus, the decoding can be performed completely inparallel without memory clashes.

As noted above, the calculation index calculations simplifysignificantly in an embodiment where the interleaver is size N n*m andm=2n, each memory simply stores the a set of N/M addresses (where Mdivides evenly into M). Thus the index is the address N divided by thesubsection length M.

FIG. 5 is a block diagram of a portion of a turbo decoder configured inaccordance with one embodiment of the present invention. As well knownin turbo decoding, the extrinsic information is generated by the decoderduring a first subiteration, and then that extrinsic information isreused in interleaved order by the decoder during a second subiteration.

During operation, an interleaved subiteration begins by the generationof a vector of addresses by address vector generator 506(a). Addressvector generator generates M address, where M is the number of decodingunits, and which in the exemplary embodiment is 4. The four addressescorrespond to the i^(th) address in each of the four subsections of theinterleaver.

The address vector is received by address routing circuit 504(a).Additionally, one of the addresses is routed to routing selector circuit508(a). Routing selector circuit 508(a) determines the particular indexassociated with the received address, and forwards that address toaddress routing circuit 504(a) and data routing circuit 500(a).

In the described embodiment, the index of the other subsections can bedetermined based on the index of any one subsection. In particular, ifthe index for the first one subsection is j, then the indexes for thenext three subsections are (j+1)% M, (j+2)% M, and (j+3)% M. Thus, onlyone routing selector circuit 508(a) is necessary for each set of routingcircuits. In other embodiments of the invention this property may not bepresent (for example when memory interleavers are being used), and onerouting circuit for each address in the address vector will benecessary.

Address routing circuit 504(a) receives the address vector and therouting index, and reroutes the addresses into a new address vectorbased on the index. Thus, if the index is 2, the first address is routedto the second memory, and the remain addresses are rerouting based onthe other index calculation described above. The addresses are receivedby the extrinsic memories 502, which output the corresponding data todata routing circuit 500(a).

Data routing circuit 500(a) receives the data and routes it to thedecoder for which the corresponding address was generated based on theindex from routing selector 508(a). The resulting data vector orextrinsic information is received by the decoders (not shown) whichperform decoding using the extrinsic information as well as the receivesamples (not shown).

After some processing delay, the decoders generate new extrinsicinformation that is received by data routing circuit 500(b). As the newextrinsic information is received, address vector generator 506(b)generates the address vector for the interleaver, and the address vectoris received by address routing circuit 504(b) and routing selector508(b) receives one of the addresses.

Routing selector 508(b) determines the index for one address, and thatindex is supplied to address routing circuit 504(b) and data routingcircuit 500(b). Data routing circuit 500(b) routes the interleavedextrinsic information generated during the decoding to the properextrinsic memory 502, and address routing circuit 504(b) routes theinterleaver address vector to those extrinsic memories 502 as well. Thedata is then written in non-interleaved order for processing during thenext subiteration.

FIGS. 6A and 6B show an iterative decoder configured in accordance withan alternative embodiment of the invention in which a non-indexedinterleaver is used. In some instances, a non-index interleaver may berequired to meet preexisting specifications or for performance reasons.

Referring now to FIGS. 6A and 6B, receive samples are received by LLRflow control 100. LLR flow control receives samples in sets of between 1and 4. These set correspond to different modulation scheme such as BPSK(1 sample per set) QPSK (2 samples per set), 8PSK (3 sample per set) and16QAM (4 samples per set). LLR flow control writes out samples in pairsto sample bank (sbank) interface 102.

Sbank interface simultaneously writes in sample pairs to one of thesample memory banks (sbank0 and sbank1) while reading out sixteen setsof sample pairs from the other sample memory bank.

Multiplexer 104 receives the sixteen sets of sample pairs from sbankinterface 102 and also receives sixteen set of soft decision data fromAPP memory 300. During a first mode, multiplexer 104 supplies the samplebank data to depuncture circuit 108 and during a second mode multiplexer102 supplies the soft decision data to depuncture circuit 108. The firstmode is preferably parallel concatenated convolutional (PCCC) mode aswell as the outer code for serial concatenated convolutional (SCCC) modeand the second mode is for inner codes of serial concatenatedconvolutional mode.

Depuncture circuit 108 inserts puncture values according to a puncturepattern and add app 110 receives the depunctured values from depuncturecircuit 108 as well as extrinsic information from extrinsic memories300. During the first iteration of SCCC decoding the extrinsicinformation is not supplied during the inner code processing. Also, theouter most code of SCCC processing does not use extrinsic information.PCCC decoding and the inner code of SCCC decoding for iterations greaterthan one use extrinsic information. Additionally, middle codes of 3 codeSCCC will also use extrinsic information for iterations greater thanone.

In an exemplary embodiment, the samples stored in the sbank memories andthe extrinsic memories are divided into 16 subsections. The subsectionare preferably divided in the order received, so that each subsection isapproximately one sixteenth of the frame being decoded, and the secondsubsection follows the first and the third follows the second, etc.

Each subsection of the sample bank memory is decoded by a MAP decoderwithin MAP engine 120. A MAP decoder is a decoder that performs themaximum a posteriori decoding algorithm. During a warm up period, thelast portion of the previous subsection is read into the particulardecoder performing the decoding for that section. This is accomplishedby reading out the end of each subsection from each sbank subbank andfrom each extrinsic subbank, and then rotating, or shifting, the outputof this read using rotate circuit 114. Typically the warm up periodtakes 32 decoding cycles.

Once the warm up period has been competed each subsection of data isapplied to a particular MAP decoder within MAP engine 120. MAP enginepreferably performs decoding using a sliding window algorithm to reducethe amount of state memory necessary to perform the decoding.Additionally, MAP engine preferably contains local cache memories tostore the values being decoded so that multiple passes can be made overthe values in accordance with the MAP decoding algorithm.

To read out extrinsic information from extrinsic memory 300 (also calledAPP memory because it contains a posteriori information), a specialdeinterleaver circuit is used.

The interleaver addresses are generated by either a memory basedinterleaver (mem_pi) 301 or a generator function (gen_pi). Theinterleaver circuits output 16 memory addresses, which correspond to the16 MAP queues that will be performing the decoding. The interleaveraddresses are received by clash check circuit 310, which determines theextrinsic memory bank in which data associated with that address isstored.

In accordance with the indexed interleaver circuit described above, theuse of clash check would be eliminated and overall efficiency increased.

When multiple requests are received for the same memory bank, clashcheck select one request and queues up the other requests. Duringsubsequent clock cycles multiple requests for the same memory bank arearbitrated based on the queue size from which the request originates.

Clash check generates addresses which are forwarded to the extrinsicmemory, and also generates an enable vector and a routing vector, bothof which are forward to data-buff-in circuit 330. The enable vectortells data buff in which pipeline were selected, or “won”, in thearbitration process, and therefore should be read into the data buffer.The routing vector tells which extrinsic memory bank will be supplyingthe data to that MAP queue.

Data buff in assembles the data from extrinsic memory 300 into completerows of sixteen, and forward the complete row to add app circuit 110where they are added with the sample data or other decode data.

MAP engine 120 simultaneously decodes the sixteen subsections of theframe and outputs extrinsic as well as soft decision data. Extrinsicinformation is received by data buff out, which also receives therouting vectors and valid vectors from clash check after being delayedby FIFO's 340. Data buff out 335 deinterleaves the extrinsic data byrouting to extrinsic memory 300 according to the routing and enablevectors, and by also routing the enable signals themselves according tothe routing vector. Extrinsic memory 300 receives the address vectorafter also being delayed by a FIFO, and writes the values from data buffout based on those addresses as well as enable signals forwarded formdata buff out. Data buff out is used during PCCC decoding as well asduring the SCCC codes for codes other than the outer most code.

Puncture circuit 350 receives soft decision values from MAP engine 120including systematic and parity soft decision values. Puncture circuit350 punctures out values according to a puncture pattern, and suppliesthe punctured data to extrinsic memory 300. The punctured values arepreferable written in the order that they are generated, and thus nodeinterleaving is necessary.

Puncture circuit 350 is used for the outer codes in SCCC decoding andthe values generated are used as the extrinsic information during thedecoding of the more inner code.

In the exemplary embodiment shown, the extrinsic memory is comprised offour banks. These four banks are used for performing 3 constituent codeSCCC decoding. In particular, for the middle code, one bank suppliessoft decision data, another bank receives soft decision data, a thirdbank supplies extrinsic information, and the fourth bank receivesextrinsic information.

A method apparatus for generating an interleaver, along with a systemfor performing. communication using that interleaver, is now describedin detail with respect to the exemplary embodiments of FIGS. 7-9. Inaccordance with one embodiment of the invention, a pseudo randominterleaver is generated by dividing the desired address space N into nsubsets of m values (n*m). One value from each subset is selected as aseed, creating a set of n seeds used to generate the rest of theinterleaver.

In a first exemplary embodiment, m is equal to 2n. An exemplaryinterleaver of size 15488 (N) is generated, corresponding to a value nof 88 and a value m of 176. In accordance with the exemplary embodiment,the set of 15488 addresses is divided into n subsets, where the subsetsare defined by the result of dividing the interleaver address values bythe modulo-n of the address. Additionally, the address are alsocategorized by an “n-multiple”, which is the number of times n can bedivided into the address. In the exemplary case of n=88, there are 88possible modulo-n values and 176 possible n-multiple values in theaddress space of 15488. For example, the value 1000 has a modulo-n of 32(1000% 88), and its n-multiple is 11 (1000/88). The value 12523 has amodulo-n of 27 and an n-multiple of 143.

While there are many other techniques for dividing the address spaceinto subsets (some of which are described below), the use of themodulo-n index provides many advantages. In particular, the used of themodulo-n index causes all the values within the subset to be equallyspaced, thus ensuring a minimum distance of n between any to point inthe subsets regardless of the order of the values within the subset.Using the modulo-n values of the addresses to define the subsets alsoallows the entire subset to be generated by just specifying the modulo-nvalue of the subset, or by just supplying one value from the subset.Additionally, the minimum distance is the same for each subset (with theminimum distance being equal to n), further simplifying generation ofthe entire interleaver as described in greater detail below.

Additionally, if one (seed) value from any subset is provided, the restof that subset may be generated by adding n to the seed value and takingthe result modulo-N. For example, if the seed value is 500, then theseries 500, 588, 676 . . . 412 represents one modulo-n subset. Othermethods for defining subsets, and therefore for generating all theaddresses in the subset, are consistent with the use of the presentinvention including, for example, forming a series by adding p*n to theseed value (modulo-N), where p is relatively prime to n.

Thus, in the current embodiment of the invention the entire addressspace for the n*m interleaver (where n=88 and m=176) is divided into 88subsets defined by the modulo-88 value of each address. Once the subsetsare defined, one value is selected from each subset and placed in aparticular order to form the seeds for the interleaver.

In accordance with a first embodiment of the invention, the seeds areselected so that no two seeds have the same or adjacent n-multiplevalues. In the case where m=2n, the n-multiple values of the seeds mustbe either all even, or all odd, in order to satisfy this condition.

Finally, the selected seeds are placed in a particular order. Inaccordance with a first embodiment of the invention, the seeds areordered so that the n-modulo value is within d of the location of theseed within the set, with at least one seed placed out of order withrespect to its modulo-n value. For example, given a value d of 10, theseed with the n-modulo index of 0 must be in located among the first 10seeds in the set. A seed with a modulo-n index of 18 could be located atany location between 0 and 36. This seed configuration is used when theentire interleaver is generated by repeatedly adding n to the seed setand taking the result modulo-N (N−15488).

In an alternative embodiment of the invention, the seeds are placed inreverse order with respect to their modulo-n value, offset by a ditheramount less than or equal to n. Thus, for a d of 10, a seed with amodulo-n value of 87 can be placed in anyone of the first 10 locations.Once the seeds are configured, the rest of the interleaver is generatedby repeatedly modulo-N subtracting n from each seed until 15488 valueshave been generated.

For either embodiment, for a given value d, the location of the seedsshould preferably minimize the duplication of offset values. That is,the amount of dithering should be spread across the dither value d asmuch as possible. For example, with a d of 10, there are 11 possibleoffset values 0-10. With 88 seeds, maximum dithering will move 8 seedsby 0, 8 seeds by 1, 8 seeds by 2 and so on, with the final 8 seedsoffset by 10. Typically, a random dithering will come naturally comeclose to this result, and is sufficient for good performance based onthe selection of d.

Moving the seeds from their natural modulo-n based order increases theoverall randomness of the interleaver substantially with only arelatively small reduction in spreading. Increased randomness improvedthe performance of a turbo code employing the interleaver, particularlyfor frames greater than 4000 bits, but some improvement is also seen forframes as large as 1000 bits.

In general, the only restriction on d is that it be greater then 1,although some ranges tend to give better performance than others. Forexample, d is typically selected to be between 10-70% of n. For smallerinterleavers it is often useful to keep d smaller to preserve more ofthe spreading property of the interleaver. Typically, d should be set sothat a target spread of at least 25 is maintained.

For larger frames higher values of d are preferable, as more randomnessis desirable. Typically, d-will be 50% of n for interleavers havinggreater than 10,000 addresses. This amount of dither preserves spreadingwhile also increase randomness and therefore the rate of convergencewhen incorporated into a turbo code.

In a preferred embodiment of the invention, the seeds form the first naddresses in the interleaver. The rest of the interleaver is generatedby adding n (modulo-N) to the previous n addresses. In the exemplarycase, this results in 175 additional sets of 88 address for a total of15488 addresses. Alternatively, the rest of the interleaver can begenerated by subtracting n (modulo-N, wrapping around for values <0)from the previous n addresses.

In other embodiments of the invention, integer multiples of n can beadded to the seeds, or a number q can be added where q is relativelyprime to n or equal to one. However, the spreading for these otherembodiments can be reduced too substantially for many incrementingvalues and therefore searching is typically required to confirm suitablespreading can achieved for some interleaver sizes and incrementcombinations.

While many interleaver sizes will work in different embodiments of theinvention, 15488 is an excellent frame length for a variety of reasons.In particular, it is evenly divisible by many powers of 2, including 2,4, 8 and 16, facilitating the division of the frame into separate partsfor parallel decoding. A system and method for performing such decodingis described in co-pending U.S. patent application Ser. No. 60/174,290incorporated herein by reference, and the co-pending applicationclaiming priority thereto (attorney docket number P002-APP) entitledSystem and Method for Efficient Processing of Turbo Codes.

Additionally, 15488 is not a multiple of 3, 7 or 15. The numbers 3, 7and 15 are typical periods for various constituent encoders, including4, 8 and 16 state encoders. In order to perform tail biting the lengthof the frame cannot be an even multiple of these numbers, and thereforethis frame length provides the flexibility to be used with the mostcommonly used constituent encoders.

A more detailed description of interleaver generation process performedin accordance with one embodiment of the invention is described for amuch smaller interleaver.

Table. I shows the beginning of the seed generation process for aninterleaver of size n*m, where n=8 and m=16, for a total interleaversize N=128. In Table I a set of seeds (left-most column) are generatedbased on a set of modulo-n values (column 2) and n-multiple values(column 3). The seed values are equal to the modulo-n value+n*n-multiplevalue (seed=modulo-n+[n*n-multiple]) which is listed in the right-mostcolumn.

As described above, the n-multiple values are selected so that no twovalues are the same or offset by one. In this case all the n-multiplevalues are all even, but using all odd n-multiple values would alsosatisfy this condition. As listed in Table I, the modulo-n values areplaced in order of their location, and the n-multiple values are alsolisted from smallest to greatest. TABLE I Location Modulo-n n-multipleseeds 0 0 0 0 1 1 2 17 2 2 4 34 3 3 6 51 4 4 8 68 5 5 10 85 6 6 12 102 77 14 119

In accordance with one embodiment of the invention, the n-multiples arefirst shuffled in random order, yielding the results of Table II. TABLEII Location Modulo-n n-multiple Seeds 0 0 6 48 1 1 12 97 2 2 4 34 3 3 1083 4 4 14 116 5 5 2 21 6 6 0 6 7 7 8 71

Addtionally, the modulo-n values are shuffled with the restriction thatno value be moved more than an amount d relative to its location withinthe set of seeds. Table III illustrates an exemplary shuffling of themodulo-n values with a value d=2. As illustrated in Table III, eachmodulo-n value is shifted by either 0, 1 or 2 relative to its locationwithin the sets of 8 seeds. For example, modulo-n value 4 is placed atlocation 3, just 1 away from location 4, and the modulo-n value of 2 isplaced at location 0, just 2 away from location 2. As noted above, themodulo-n values may also be listed in decreasing order from 7 to 0, andmay also have a wrap around configuration starting at some middle valueand incrementing or decrementing. TABLE III Location Modulo-n n-multipleSeeds 0 2 6 50 1 1 12 97 2 0 4 32 3 4 10 84 4 3 14 115 5 7 2 23 6 5 0 57 6 8 70

The resulting seeds shown in Table III can be used to generate theinterleaver of size N=128 by using the seeds as the first 8 values ofthe interleaver. The next set of 8 addresses are generated by modulo-128adding n (n=8) to the set of 8 seeds. The next set of 8 address aregenerated by modulo-128 adding 8 to the previous set of 8 addresses.This is repeated until 128 addresses are generated. In an ASIC, theinterleaver can be generated by simply storing the n seed values.

The resulting interleaver will have a spread slightly less than 16(which is equal to m). As d is increased the 16 will typically decreasebut randomness will increase. The N=128 interleaver described above isprovided for purposes of illustration, as turbo codes employinginterleavers of size 128 will typically not benefit significantly from ad greater than 1. The performance improvement in a turbo code from a dgreater than 1 will increase as the size of the interleaver increases.

The above described embodiment of the invention works best when m istwice m (m=2*n), and typically interleavers of this size provide thebest spreading properties. However, for many applications, frames sizesthan can not be formed by an combination of n*m where n and m areintegers and m is 2*n. Additionally, some applications benefit frominterleavers with more randomness than can be provided from the maximumdithering available in the above-described embodiment of the invention.

In an alternative embodiment of the invention, and interleaver of sizen*m can be constructed for any m greater than or equal to n. In thisembodiment of the invention, the set of seeds are constructed in similarfashion to the first interleaver, except the n-multiple values of theseeds can be adjacent rather then separated by a value of 1. Thus, theset of n-multiple values used to construct the interleaver will not beall odd or all even numbers.

The remaining seed and interleaver generation process is substantiallythe same as the previously described interleaver, including thedithering process. In this embodiment, the higher number of seedvalues—relative to the entire interleaver—typically provides greaterrandomness than a similarly sized interleaver with fewer seed values.Additionally, the greater variance in the distance between the seedvalues also adds increased randomness. This inherent increase inrandomness typically reduces the amount of additional ditheringnecessary. For example, a dither value of d between 1 and 40% of ntypically provides sufficient randomness in this embodiment of theinvention, with dithering of as little as 10% very good performanceincreases for frames larger than 1000 addresses.

In still another embodiment of the invention, interleavers of size n*mcan be generated for any integer value of n and m. In this embodiment ofthe invention, the generation of the seeds proceeds somewhat differentlythan the previous two embodiments of the invention.

In accordance with this embodiment of the invention, the set of n seedsare generated based on a seed_step factor, where seed_step an integernumber relatively prime to n. To determine the best value of seed_stepsome searching may be required. For m less than n, a seed_step that isthe closest relatively prime integer m is typically suitable. Forexample, for an n of 8 and an m of 4, a suitable seed_step value wouldbe 5.

Once the seed_step value has been selected a set of n seed_stepmultipliers are generated in random order by generating a set ofintegers between 0 and (n-1). These integers are then multiplied by seedstep to generate the set of n seeds. Table IV illustrates the generationof 8 seeds that can be used in an 8 by 4 interleaver using a seed_stepof 5. TABLE IV Location seed_step Seed_step multiplier Seed 0 5 4 20 1 51 5 2 5 6 30 3 5 5 25 4 5 3 15 5 5 7 35 6 5 2 10 7 5 0 0

In a preferred embodiment of the invention, the seeds are used as thefirst set of n addresses. The next set of addresses are generated byadding a value set_step to the seeds, and then the remaining sets ofaddress (in this case two more sets) are generated by adding (modulo-N)set_step to the previous set of addresses. Set_step is preferablyselected so that it is relatively prime to both n and m. Additionally,when m is less than n, set_step is preferably chosen so that it is alsoclose to n/2 while remaining relatively prime to n and m. In some casessearching is required for set step, but typically a value between 1 and2n will yield a spreading amount of at least m/2.

This interleaver typically produces more randomization and lessspreading relative to the two other methods described above, andtypically no additional dithering is required

In still another embodiment of the invention, an n*m interleaver isgenerated by dividing the total interleaver address space into n spacescomprised of the first m addresses, then next m addresses, up to the nthset of m addresses. One value from each of these sets is selected forthe seed set and ordered so that the resulting seed set has a minimumspreading distance of s where s is preferably greater than m/2. Thisseed set is used as the first set of n addresses in the interleaver.

In one embodiment of the invention, the next set of addresses isgenerated by adding a factor f to each seed, where f is i* set_stepmodulo-m ([i*set_step] % m), where set_step is relative prime to m. Thevalue i is the index of the set of addresses being generated.

Table V illustrates the generation of a 32 address 8*4 interleaver.Addresses 0-7 are the seed values, and set step is equal to 3. TABLE VAddresses 0 1 2 3 4 5 6 7 i f 0-7 0 24 16 4 28 8 12 20 0  8-15 3 27 19 731 11 15 23 1 3 16-23 2 26 18 6 30 10 14 22 2 2 24-31 1 25 17 5 29 9 1321 3 1

Other embodiments of the invention comprise dividing the address spaceinto n subsets, where the subsets maybe generated on the fly using amathematical operation or small look-up table. One address from eachsubset is then selected and ordered so that the spread of the resultingcross set is above a threshold that is typically greater than 20 or(N/2)² (where N is the size of the interleaver) whichever is less, andso that the resulting set of address has significant randomness.

These addresses are then used as the first set of addresses in theinterleaver. The remaining addresses are generated so that the spreadingdistance in the first set is substantially preserved resulting in ahighly spread random interleaver that can be used in a turbo code.

As should be apparent, the various embodiments of the invention describen*m interleavers generated using n seeds, where the seeds form the firstn addresses in the interleaver. Those skilled in the art will recognizethat alternative embodiments of the invention may use m seeds, whereeach seed defines a set of n addresses. In this embodiment, the firstseed defines the first n addresses, which are generated based on thatseed (the seed itself can be used as an address, but does not have tobe).

The first set of addresses are typically generated using a pseudo randomfunction such as a congruential series using relative prime increments,selected to provide sufficient spreading between the addresses. Anothermethod that ensures proper spacing is to use the pseudo random functiongenerator to generate the n-multiple values, and then multiply thosevalues by n to determine the addresses.

Once the first set of addresses are generated using the first seed, thenext set of addresses are generated using the next seed, typically usingthe same pseudo random function, but not necessarily. The seeds aretypically chosen so that spreading distance is maintained acrossmultiple sets of addresses. If the same pseudo random function is used,this typically only requires the difference between any two adjacentseeds (preferably including wrap around from the last to the first seed)be greater than the minimum spreading distance within any set ofaddresses in order to preserve the overall spreading distance.Preserving the spreading distance can also be achieved by limiting thespacing of the seeds to some multiple of n.

In a more general embodiment of the invention, the entire set ofinterleaver addresses (the interleaver address space) is divided into nsubsets of addresses. The n subsets are preferably substantially equallyspaced. For example, the subsets may be defined different modulo-nindexes as done in at least of the embodiments described above.Alternatively, the subsets may be defined as portions of relative primesequences, each sequence using a different starting index, as done atleast one other embodiment of the invention described above.

Many other methods for generated substantially equal spaced subsets ofaddresses can be employed in alternative embodiments of the invention.However, the various embodiments provided herein allow for a range ofspreading, randomness, flexibility and randomness tradeoffs.

Typically, making the subsets substantially equally spaced means theaddresses are substantially equally spaced with respect to the otheraddresses within the subset. For example, the address may all bemultiples of some number, or may be some consecutive portion of thetotal address space. Alternatively, the addresses may only be evenlyspaced with respect to the addresses in the other subsets. Thus, whilethe addresses within a particular subset have varied separation from oneanother, the variation of address separation within the other subsets issubstantially similar.

Once the interleaver address space has been divided into a set ofsubstantially equally spaced subsets, a set of seed values are thenselected. The seed values are selected so that the set of seeds has aminimum spreading value, and so that the spreading value issubstantially maintained when the remaining sets are generated based onthe seed values.

Once again, various methods for achieving this result have beendescribed above. In general, a set of seeds are selected based on arandomly chosen set of multiples of the row size m. The spacing of theseeds is then selected so that the subsequent sets will remain wellspread with respect to the previous set.

FIG. 7 is a block diagram of a turbo encoder and decoder configured inaccordance with one embodiment of the invention. Information bits to betransmitted and encoded are received by constituent encoder 708 andmemory 702. In the described embodiment of the invention, theinformation bits are written into memory 702 while being addressed bycounter 720. Once a frame of data has been written in the informationbits are read out from memory 702 while being addressed by addressgenerator 722.

In the described embodiment, address generator 722 generates a series ofinterleaved addresses in accordance with the above described invention,typically using the seeds stored in seed ROM 724. Thus, the informationbits are read out of memory, and therefore received by constituentencoder 704, in interleaved order.

In a first described embodiment of the invention, constituent encoder708 receives the information bits in non-interleaved order and performsconvolutional encoding on those information bits. When usinginterleavers generating in accordance with the above describedinvention, convolutional encoder 708 is preferably a rate 1/2 systematicrecursive convolution code. Rate 1/2 codes benefit from the increasedspreading characteristic of the present invention, and are relativelysimple to implement when compared to encoders with higher natural rates.However, other natural rate encoders may be employed with theinterleavers constructed in accordance with the invention.

In this first embodiment of the invention, constituent encoder 708performs a first encoding of the non-interleaved information bits. Oncethe entire frame of data has been encoded, the state information withconstituent encoder 708 is received by initialization state calculator(init state calculator) 707. Init state calculator 707 receives theinitialization state and calculates a starting initialization state.

Once the starting state has been set, the frame is then encoded a secondtime. During this second encoding, the state of constituent encoder 708is initialized using the initialization state calculated by init statecalculator 707. The information bits are then encoded from memory 701 asecond time, and the resulting code symbols are received by multiplexer706. The systematic bits 730 are also forwarded for transmission.

Similarly, constituent encoder 704 performs two encodings on interleavedinformation bits received from memory 702. After the first encoding, thefinal state of constituent encoder 704 is received by init statecalculator 705. Init state calculator 705 calculates an initializationstate based on the final state received. The state of constituentencoder 704 is then initialized to the initialization state calculatedby init state calculator 705. Once initialized, constituent encoder 704performs the second encoding on the interleaved information bits frommemory 102, and the resulting code symbols are received by multiplexer706.

Multiplexer 706 orders and punctures code symbols from the two encodersin order to generate the desired level of coding. The resulting codesymbols and systematic bits 730 are then forwarded for transmission.

By using a code comprised of a highly spread generatable interleaver incombination with a 16 state code and a described interleaver

The use of either init state calculators 703 or 707, or both, may beomitted in alternative embodiments of the invention. However, this willtypically reduce overall performance of the code because the two codesare not terminated. Alternatively, one of the two codes (typically thefirst) may be terminated by adding flush bits to the end of theinformation bits. However, the additional bits reduce throughputrelative to the use of init state calculators 703 and 707. A descriptionof tail biting can be found in the paper Weiβ, Ch.; Bettstetter, Ch.;Riedel, S.: Turbo Decoding with Tail-Biting Trellises. In: Proc. 1998URSI International Symposium on Signals, Systems, and Electronics, 29.Sep.-2. Oct. 1998, Pisa, Italien, pp. 343-348.

To perform tail biting for encoders with feedback (which include therecursive systematic convolution codes described herein), the endingstate X_(N) depends on the entire information vector u encoded. Thus,for a given input frame, the initial state x₀ must be calculated, wherex₀ will lead to the same state after N cycles.

This is solved by using the state space representation:xt+1=Ax _(t) +BU _(T,t)  (1)vT,t=Cx _(t) +Du _(T,t)  (2)

of the encoder. The complete solution of (1) is calculated by thesuperposition of the zero-input solution x[zi],t and the zero-statesolution x[zs],t:xt=x _([zi],t) +X _(t,[zs]) =A _(t) x ₀+sum_((j=0−>t−1))A ^((t−1)−j) Bu_(T,t)  (3)

By setting the state at time t=N equal to the initial state x₀, weobtain from (3) the equation(A ^(N) +I _(m))X₀ =X _([zs],N)  (4)

where I_(m) denotes the (m x m) identity matrix. If the matrix (Z_(n)_(—) I_(m)) is invertible, the correct initial state x₀ can becalculated knowing the zero state response X_([zs],N)

Based on this logic, the encoding process should be done in two steps:

The first step is to determine the zero-state response X_([zs],N) for agiven information vector u. The encoder starts in the all-zero statex₀=0; all N k₀ information bits are input, and the output bits areignored. After N cycles the encoder is in the state X_([zs],N). We cancalculate the corresponding initial state x₀ using (4) and initializethe encoder accordingly.

The second state is the actual encoding. The encoder starts in thecorrect initial state x₀; the information vector u is input and a validcodeword v results.

In one embodiment of the invention the precomputed solutions to (4) forthe desired frame size N (or sizes) can be stored in a look-up table.

FIG. 8 is a block diagram of a turbo decoder configured in accordancewith one embodiment of the invention. After transmission through achannel (which typically introduces errors) the resulting receivesamples for a frame of data are stored in memory bank 800. Memory bank800 is typically random access memory, and is typically double bufferedso that one frame of data can be decoded while another frame is beingreceived.

For higher order modulation schemes the samples are preferably storedand converted to log-likelihood ratios (LLR) during each decoding asdescribed in copending U.S. patent application Ser. No. 60/256,890entitled “Reduced Memory Storage in an Iterative Decoder” and filed onDec. 18, 2000, now abandoned, assigned to the assignee of the presentinvention and incorporated herein by reference in its entirety.

During decoding, a first subiteration (in accordance with the firstconstituent code of the turbo code) is performed the LLR values (eitherstored or calculated on the fly from the samples) are fed through sumcircuit 802 to log-MAP decoder 804. The use of log-MAP decoder 802 isgenerally preferred as it provides excellent performance with reducedcomplexity, however, other types of soft-in-soft-out (SISO) decoders maybe employed.

During the first decoding iteration, sum circuit 802 simply passes theLLR values to log-MAP decoder 804. The resulting extrinsic informationfrom log-MAP decoder 804 is stored in extrinsic information memory 806.

In an embodimemt of the invention in which tail biting is employed,log-MAP decoder will receive the end of the frame of data to be decodedbefore beginning to decode at the start of the frame. By decoding theend of the frame first, the encoder will be placed in the start stateused during the original decoding as the start state and finish stateare the same. This “warm up” should be used during each iteration forwhich the corresponding constituent code employs tail biting.

Once the first iteration has been completed a second subiteration isperformed (in accordance with the second constituent code of the turbocode) by summing the extrinsic information from extrinsic informationmemory 806 with the corresponding LLRs from sample memory 800. Theresulting “corrected” LLR values are fed to the log-MAP decoder 804.(Where constituent codes having different parameters are used, log-MAPdecoder should be configurable or multiple instantiations should beused.)

The extrinsic information is read from extrinsic information memory 806using address generator 808. Address generator 808 generates interleavedaddresses using seed values from seed read-only-memory (ROM) 810 inaccordance with the above described interleaver generation schemes.Thus, the extrinsic information is read out in interleaved order to becombined with the interleaved samples within sample memory 800.

Log-MAP decoder 804 decodes the corrected LLR values generating newextrinsic information that is stored within extrinsic information memory806. This extrinsic information is used during the next subiteration(which for a 2 constituent code based turbo code will typicallycorrespond to the first constituent code) where it is summed with theLLR values and then decoded again by log-MAP decoder 806. During thissecond iteration the extrinsic information is read out using counter 808and therefore in non-interleaved order.

FIG. 9 is a flow chart illustrating the generation of the interleaveraddresses in accordance with one embodiment of the invention. Theinterleaver generation process begins at step 900, and at step 902 thefirst set of n addresses are calculated based on the seed values.Typically, the seed values are in fact the first set of addresses, butthe seed values may also be used indirectly to calculate the first setof addresses.

Once the first set of addresses have been calculated the next set ofaddresses are calculated at step 904 based on the previous set, which inthis case is the first set. As described above, calculating the next setof addresses typically involves adding an increment value to theprevious set of addresses, although other calculation methods areconsistent with the use of the invention.

Once the next set of addresses are calculated at step 904, it isdetermined at step 906 if the entire interleaver has been generated. Ifnot, step 904 is performed again and the next set of addresses arecalculated based on the previous set of addresses. If the entireinterleaver has been generated, then the generation process ends at step908.

The above described coding scheme provides excellent forward errorcorrection performance including improved error floor performance withreduced circuit area due to the use of generatable interleavers havingan excellent combination of spreading and randomness properties.Additionally, some embodiments of the invention allow for a wide rangeof interleaver sizes, which is beneficial when interfacing with othersystems or standards that have particular requirements.

Particularly good performance is achieved with a code that combines thedescribed interleavers with tail bitten (or terminated) rate 1/2 codes.The rate 1/2 codes can be a varying states depending on the level ofperformance required, but the use of a 2 constituent codes in theparallel concatenation (PCCC) scheme described herein gives a highlydesirable error floor with 16 state constituent codes (four memoryelements). For example, a PCCC using a generatable interleaver asdescribed above and 16 state rate 1/2 constituent codes can providebetter than 10e-10 bits/sec (BER) performance in a rate 2/3 turbo codeemploying 8PSK modulation. A BER of 10e-10 is minimum requirement formany applications including video broadcast.

The above described codes can also be used within Turbo Codes describedin co-pending U.S. provisional patent application Ser. No. 60/202,337entitled “Improved Error Floor Turbo Codes” incorporated herein byreference in its entirety. As described in that patent, high performanceinterleavers are generated using three or more constituent codes and twoor more interleavers.

In accordance with this embodiment of the invention, at least one of theinterleavers used in the code is a highly randomized generatableinterleaver configured in accordance with the interleaver generationprincipals set forth in the high spread patent.

In another embodiment of the invention, both interleavers are highlyrandomized generatable interleavers configured in accordance with theinterleaver generation principals set forth in the high spread patent.In this embodiment of the invention, some particularly good combinationsexist.

In a first combination, two interleavers of size n*m, where m=2n areused. In accordance with the interleaver generation techniques set forthin the high spread patent, one interleaver is defined by a set of n seedvalues to which a value is repeatedly added to generate the remainingaddresses and the interleaver is defined by a set of n seed values towhich a value is repeatedly subtracted to generate the remainingaddresses. Preferably each interleaver is also dithered as described inthe high spread patent. Simulation has shown that this interleavercombination works well with a turbo code comprised of two 8 state codesand one 4 state code, although performance with many other codes is alsovery good.

In a second combination, one interleaver is comprised of an interleaverof size n*m where m is at least larger than m and preferably 2m. Theinterleaver is then constructed by adding (or subtracting ) n to the setof seed values. The second interleaver is size n*m, where m is less thanm, however. Thus the second interleaver will have a smaller spread andincreased randomness with respect to the first interleaver. Thiscombination of a highly spread less random interleaver with a morerandom less spread interleaver produces excellent results, particularlywith may lower complexity code combinations.

For example, when combined with a very simple code comprised of all fourstate constituent codes, this interleaver combination can achieve biterror rates as low as 10e-10 for a rate 2/3 8psk code for frame sizeof >10,000 bits. Achieving error rates this low using very simpleconstituent codes and generated interleavers provides a highly efficientand economical coding scheme that will allow the benefits of turbocoding to be incorporated into many applications.

To support local area network traffic that may include audio and videoit is useful to have packet sizes such as 4608, 4160 information bitsfor data traffic, and a 128 bit packet for control information. Toimplement these frame sizes with a Turbo Codes that use a duo-binaryconstituent codes, which process two bits per cycle, interleavers ofsizes 2304, 2080 and 64 addresses are required.

To form an interleaver with 2304 addresses in accordance with oneembodiment of the invention an interleaver that uses the nm method ofgeneration may be employed. For a 2304 address interleaver both n and mmay be equal to 48. Additionally, set_step may also be equal to 48. Fora 2080 address interleaver n may be equal to 40, m equal to 52 andset_step equal to 40. For a 64 address interleaver, n, m and set stepare equal to 8.

In one embodiment of the invention, the interleavers are generated bysubtracting set_step from the set of seeds, with numbers less than 0wrapping around modulo the total address space (2304, 2080, 1506 or 64addresses in the exemplary cases).

Table VI shows the seeds for the three interleavers described herein.TABLE VI Interleaver Seed Table Values Location 2304 2080 1056 64 0 13391558 329 54 1 809 1239 460 23 2 1434 315 679 61 3 183 1114 194 12 4 863437 807 35 5 2301 956 105 2 6 478 871 762 40 7 1668 790 632 8 1772 833848 9 1477 1152 57 10 38 147 362 11 2104 506 143 12 226 589 887 13 275388 710 14 1611 1584 272 15 989 265 581 16 2188 981 401 17 1513 220 22318 1952 1183 926 19 1135 102 488 20 2145 1258 1 21 1080 1019 528 22 10381296 23 1706 737 24 1169 694 25 880 1495 26 1794 612 27 1220 453 28 6371049 29 1269 1450 30 407 531 31 1366 47 32 732 1368 33 59 645 34 115 16635 591 322 36 494 1323 37 1541 1404 38 920 0 39 537 881 40 337 41 201842 298 43 672 44 1971 45 1830 46 2215 47 1876

The three columns in Table VI contain the seeds used to generate threeexemplary interleavers. To generate the next set of n addresses thevalue set_step as specified above is subtracted from the seeds.Additional sets of n addresses are then generated by subtracting setstep from the previous set of n addresses until the complete interleaverhas been generated. In an alternative embodiment of the inventionset_step could be added, rather than subtracted, to get each new set ofaddresses.

For example, for the 2304 address interleaver the first 48 address arethe set of seeds specified in Table VI. The next 48 address are the setof seeds minus set_step module the frame size (2304). For example,address number 58 (starting with index 0) is (38−48)+2304=2994. The 2304is added to perform the module-2994 underflow operation. For purposes ofthis application modulo include modulo underflow operations as describedin this paragraph unless expressly stated otherwise.

Table VII shows some properties regarding the seeds used in the 64address embodiment of the invention described herein. TABLE VII SeedProperty Table Location Modulo-n (8) n-multiple (8) Seed 0 6 6 54 1 7 223 2 5 7 61 3 4 1 12 4 3 4 35 5 2 0 2 6 0 5 40 7 1 3 25

As shown in Table VII, in the one embodiment of the invention the seedsare comprised of a set of values each with a unique modulo-n value andn-multiple value. The modulo n-value is kept close to natural descendingorder location of the seed with some shuffling to increase overallrandomness. In the described embodiment these properties are common tothe three sets of seeds shown in Table VI.

In the example 8 seed case, only one pair of modulo-n values areshuffled to increase randomness. In one embodiment of the invention anascending order of modulo-n values may be used.

It is also preferable to incorporate the tail biting described above forone or more of the constituent codes described above.

While the above detailed description has shown, described, and pointedout novel features of the invention as applied to various embodiments,it will be understood that various omissions, substitutions, and changesin the form and details of the device or process illustrated may be madeby those skilled in the art without departing from the invention. Theforegoing description is of the best mode presently contemplated ofcarrying out the invention. This description is in no way meant to belimiting, but rather should be taken as illustrative of the generalprinciples of the invention. The scope of the invention should bedetermined with reference to the claims.

1.-9. (canceled)
 10. A method for decoding a frame of encoded data, saidframe of encoded data having been encoded by a turbo code encoder havinga pseudo random interleaver having addresses, said method comprising thesteps of: decoding a first subsection of said frame; generating an indexvalue corresponding to an address from a first subset of said addresses,said address being associated with said first subsection; and using anextrinsic value from a set of extrinsic values for said decoding step,wherein said extrinsic value is selected from said set of extrinsicvalues based on said index value.
 11. The circuit as set forth in claim10, wherein each address from said first subset of addresses has adifferent index value and each address from said first subset ofaddresses is associated with a different subsection of said frame. 12.The method as set forth in claim 10, wherein said first subsection ofsaid frame includes a first set of continuous addresses from said pseudorandom interleaver.
 13. The method as set forth in claim 12, whereinsaid second subsection of said frame includes a second set of continuousaddresses from said random interleaver.
 14. The method as set forth inclaim 10, where said index corresponds to said address divided by a sizeof said first subsection.
 15. The method as set forth in claim 10,further comprising the step of: decoding a second subsection of saidframe, where in said step of decoding a second subsection of said frameoccurs substantially simultaneously with said step of decoding a firstsubsection of said frame.
 16. The circuit as set forth in claim 15,wherein each address from said first subset of addresses has a differentindex value and each address from said first subset of addresses isassociated with a different subsection of said frame.
 17. The method asset forth in claim 16, where said index corresponds to said addressdivided by a size of said first subsection.
 18. The method as set forthin claim 15, wherein said first subsection of said frame includes afirst set of continuous addresses from said pseudo random interleaver.19. The method as set forth in claim 15, wherein said second subsectionof said frame includes a second set of continuous addresses from saidrandom interleaver.
 20. The method as set forth in claim 15, where saidindex corresponds to said address divided by a size of said firstsubsection.
 21. The method as set forth in claim 15, wherein saiddecoding step is performed by the step of soft-in-soft-out decoding, andsaid second decoding step is performed by the step of soft-in-soft-outdecoding.
 22. The method as set forth in claim 15, wherein said decodingstep is performed by the step Maximum Aposteriori Probability decoding,and said second decoding step is performed by the step of MaximumAposteriori Probability decoding.
 23. An apparatus for decoding a frameof encoded data, said frame of encoded data having been encoded by aturbo code encoder having a pseudo random interleaver having addresses,said apparatus comprising: means for decoding a first subsection of saidframe; means for generating an index value corresponding to an addressfrom a first subset of said addresses, said address being associatedwith said first subsection; and using an extrinsic value from a set ofextrinsic values for said decoding step, wherein said extrinsic value isselected from said set of extrinsic values based on said index value.24. The circuit as set forth in claim 23, wherein each address from saidfirst subset of addresses has a different index value and each addressfrom said first subset of addresses is associated with a differentsubsection of said frame.
 25. The apparatus as set forth in claim 23,wherein said first subsection of said frame includes a first set ofcontinuous addresses from said pseudo random interleaver.
 26. Theapparatus as set forth in claim 25, wherein said second subsection ofsaid frame includes a second set of continuous addresses from saidrandom interleaver.
 27. The apparatus as set forth in claim 23, wheresaid index corresponds to said address divided by a size of said firstsubsection.
 28. The apparatus as set forth in claim 23, furthercomprising the step of: decoding a second subsection of said frame,where in said step of decoding a second subsection of said frame occurssubstantially simultaneously with said step of decoding a firstsubsection of said frame.
 29. The circuit as set forth in claim 28,wherein each address from said first subset of addresses has a differentindex value and each address from said first subset of addresses isassociated with a different subsection of said frame.
 30. The apparatusas set forth in claim 28, wherein said first subsection of said frameincludes a first set of continuous addresses from said pseudo randominterleaver.
 31. The apparatus as set forth in claim 28, wherein saidsecond subsection of said frame includes a second set of continuousaddresses from said random interleaver.
 32. The apparatus as set forthin claim 28, where said index corresponds to said address divided by asize of said first subsection.
 33. The apparatus as set forth in claim28, wherein said decoding step is performed by the step ofsoft-in-soft-out decoding, and said second decoding step is performed bythe step of soft-in-soft-out decoding.
 34. The apparatus as set forth inclaim 28, wherein said means for decoding performed Maximum AposterioriProbability decoding, and said second means for decoding performsMaximum Aposteriori Probability decoding.
 35. The apparatus as set forthin claim 28, wherein said extrinsic value was calculated during aprevious decoding of said frame of encoded data.
 36. The apparatus asset forth in claim 28, wherein said decoding step is performed usingreceived samples and said second decoding step is performed usingreceived samples.
 37. The apparatus as set forth in claim 28, whereinsaid extrinsic value was calculated during a previous decoding of saidframe of encoded data.
 38. The apparatus as set forth in claim 28,wherein said decoding step is performed using received samples and saidsecond decoding step is performed using received samples.
 39. A circuitfor decoding a frame of encoded data, said frame of encoded data havingbeen encoded by a turbo code encoder having a pseudo random interleaverhaving addresses, said circuit for decoding comprising: decoder circuitfor decoding a first subsection of said frame; index generation circuitfor generating an index value corresponding to an address from a firstsubset of said addresses, said address being associated with said firstsubsection; and routing circuit for applying an extrinsic value from aset of extrinsic values to said decoder, wherein said extrinsic value isselected from said set of extrinsic values based on said index value.40. The circuit as set forth in claim 39, wherein each address from saidfirst subset of addresses contain has a different index value and eachaddress from said first subset of addresses is associated with adifferent subsection of said frame.
 41. The circuit as set forth inclaim 39, wherein said first subsection is defined by a first portion ofaddresses from said pseudo random interleaver.
 42. The circuit as setforth in claim 41, wherein said first portion of addresses is includes acontinuous section of addresses from said pseudo random interleaver. 43.The circuit as set forth in claim 39, wherein said extrinsic value is anestimate generated during a previous decoding of said frame by saiddecoder.
 44. The circuit as set forth in claim 39, further comprising:address generation circuit for generating said address.
 45. The circuitas set forth in claim 39, wherein said extrinsic value is selected fromall extrinsic values associated with said frame based on said address.46. The circuit as set forth in claim 45, wherein said address isgenerated by adding a value to a previously calculated value, whereinsaid previously calculated value was used to generate another address insaid subsection.
 47. The circuit as set forth in claim 39, wherein saiddecoder also receives sample values representing received estimates ofsaid frame.
 48. The circuit as set forth in claim 39, wherein said indexvalue is calculated based on said address divided by a size of saidfirst subsection.
 49. The circuit as set forth in claim 39, furthercomprising: second decoder circuit for decoding a second subsection ofsaid frame.
 50. The circuit as set forth in claim 49, where said firstsubsection is comprised of a first continuous address space in saidpseudo random interleaver and said second subsection is comprised of asecond continuous address space is said pseudo random interleaver. 51.The circuit as set forth in claim 39, further comprising: memory circuitfor storing extrinsic values associated with at least said firstsubsection.
 52. The circuit as set forth in claim 49, furthercomprising: memory circuit for storing said set of extrinsic values. 53.The circuit as set forth in claim 39, wherein said decoder is asoft-in-soft-out decoder.
 54. The circuit as set forth in claim 39,where said decoder is a Maximum Aposteriori Probability decoder.
 55. Thecircuit as set forth in claim 39, wherein said first subsection is lessthan all of the frame.
 56. The circuit as set for in claim 39, wheresaid index value is calculated based on said address divided by a sizeof said first subsection.
 57. The circuit as set for in claim 40, wheresaid index value is calculated based on said address divided by a sizeof said first subsection.
 58. The circuit as set forth in claim 39,further comprising: second routing circuit for routing a new extrinsicvalue from said decoder circuit to a storage location based on saidindex value.
 59. A circuit for decoding a frame of encoded information,said frame of encoded information being encoded by a turbo code encoderhaving a pseudo random interleaver, said interleaver being comprised ofaddresses, said circuit for decoding comprising: decoder circuit fordecoding a first subsection of said frame; address generation circuitfor generation a subaddress based on an address from said addresses, andfor generating an index based on said address from said said addresses;and routing circuit for applying an extrinsic value from a set ofextrinsic values to said decoder, wherein said extrinsic value isselected from said set of extrinsic values based on said index value.60. The circuit as set forth in claim 59, wherein said subaddresscorresponds to said address modulo a size of said first subsection. 61.The circuit as set forth in claim 60, wherein said index valuecorresponds to said address divided by said size of said firstsubsection.
 62. The circuit as set forth in claim 59, wherein said firstsubsection of said frame includes a continuous section of addresses fromsaid pseudo random interleaver.
 63. The circuit as set forth in claim62, where said extrinsic value is an estimate generated circuit aprevious decoding of said frame by said decoder circuit.
 64. The circuitas set forth in claim 59, further comprising: second decoder circuit fordecoding a set subsection of said frame; second routing circuit forapplying a second extrinsic value from said set of extrinsic values tosaid second decoding, wherein said second extrinsic value is selectedbased on a second index value and said second index value is not equalto said index value.
 65. The circuit as set forth in claim 64, whereinsaid subaddress corresponds to said address modulo a size of said firstsubsection.
 66. The circuit as set forth in claim 64, wherein saidrouting circuit and said second routing circuit are multiplexors. 67.The circuit as set forth in claim 64, wherein said index valuecorresponds to said address divided by said size of said firstsubsection.
 68. The circuit as set forth in claim 64, wherein said firstsubsection of said frame includes a continuous section of addresses fromsaid pseudo random interleaver.
 69. The circuit as set forth in claim64, where said extrinsic value and said second extrinsic value areestimates generated circuit a previous decoding of said frame by saiddecoder circuit and said second decoder circuit.
 70. The circuit as setfirth in claim 59, wherein said routing circuit is a multiplexor.
 71. Aturbo code decoder circuit for decoding a frame of turbo code encodeddata, said turbo code encoded data being encoded using a pseudo randominterleaver, said turbo code decoder comprising: plurality of decodercircuits for performing decoding in response to extrinsic information;interleaver generation circuit for generating at least a subsection ofaddresses of the pseudo random interleaver, wherein said pseudorandominterleaver includes a plurality of subsections, each subsectioncontaining interleaver addresses, and wherein interleaver addresses atcorresponding locations in different subsections have different indexvalues.
 72. The turbo code decoder circuit of claim 71, wherein a firstdecoder from said plurality of decoder circuits is for decoding a firstportion of said frame corresponding to at least a first subsection fromsaid set of subsections and a second decoder from said plurality ofdecoder circuits is for decoding a second portion of said fromcorresponding to at least a second subsection from said set ofsubsections.
 73. The turbo code decoder circuit of claim 71, whereinsaid first decoder does not decode at least a portion of said secondsubsection and said second decoder does not decode a portion of saidfirst subsection.
 74. The turbo code decoder circuit of claim 71,wherein said extrinsic information comprises set of extrinsic values,said turbo code decoder further comprising: router circuit for routingat least a portion of said extrinsic values to said plurality of decodercircuits based one or more index values, said index values beingdetermined one or more addresses from said pseudo random interleaver.75. The turbo code decoder circuit of claim 74, wherein said indexvalues are based at least in part on a first subsection.
 76. The turbocode decoder circuit of claim 71, further comprising a memory circuitfor storing at least a portion of said extrinsic information.
 77. Theturbo code decoder circuit of claim 71, further comprising a pluralityof memory circuits, each for storing extrinsic information, wherein eachmemory stores extrinsic information corresponding to at least onesubsection from said set of subsections.
 78. The turbo code decodercircuit of claim 77, wherein said portion corresponds to saidsubsection.
 79. The turbo code decoder circuit of claim 71, furthercomprising a memory circuit for storing multiple subsections ofextrinsic information.
 80. The turbo code decoder circuit of claim 71,wherein each subsection from said set of subsections comprise a set ofconsecutive addresses from said pseudo random interleaver.
 81. The turbocode decoder circuit of claim 71, wherein said extrinsic information isinformation generated by at least one of said plurality of decodersduring a previous decoding of said frame.
 82. The turbo code decodercircuit of claim 71, wherein said plurality of decoder circuits aresoft-in-soft-out decoder circuits.
 83. The turbo code decoder circuit ofclaim 71, wherein a first decoder from said plurality of decodercircuits is for decoding a first portion of said frame and a seconddecoder from said plurality of decoder circuits is for decoding a secondportion of said from frame.
 84. The turbo code decoder circuit of claim71, wherein said index is said address divided by a size of saidsubsection.
 85. A decoder circuit for decoding an encoded frame of data,said encoded frame of data being encoded using a turbo code encodedhaving a pseudo random interleaver, said decoder circuit comprising:plurality of memory elements each for storing a subsection of extrinsicvalues from a frame of extrinsic values, said subsection being a portionof said frame; plurality of decoder circuits, each for receiving aportion of said extrinsic values from said frame of extrinsic values andfor decoding a portion of said frame; and at least one interleavercircuit for generating a plurality of addresses, each address having anindex value that is associated with a different memory element from saidset of memory elements.
 86. The decoder of claim 85, further comprising:router circuit for routing an extrinsic value from one of said memoryelements to one of said decoder circuits based on an index value. 87.The decoder circuit of claim 86, wherein said memory elements are staticRAMs.
 88. The decoder circuit of claim 86, wherein said index value issaid address divided by a size of said subsection.
 89. The decodercircuit of claim 86, wherein said index value is said address divided byrow size.
 90. The decoder circuit of claim 85, wherein said extrinsicinformation is a set of estimates generated during a previous decodingof said frame by said decoder.
 91. The decoder circuit of claim 85,wherein said plurality of decoder circuits further received estimatesfor at least a portion of said encoded frame of data.
 92. The decodercircuit of claim 85, further comprising: plurality of router circuitsfor routing a plurality of extrinsic values.
 93. A turbo code decoderfor performing iterative decoding of a frame of encoded data, said frameof data encoded using a pseudo random interleaver, the iterativedecoding being performed with non-interleaved subiterations andinterleaved subiterations, said turbo code decoder comprising: pluralityof decoders for decoding a plurality of subsections of said frame,wherein said subsections corresponds to subsections of said pseudorandom interleaver; interleaver circuit for generating at least onesubsection of said pseudo random interleaver; and memory circuit forstoring extrinsic information, wherein multiple subsections may be readfrom said memory circuit substantially simultaneously.
 94. The turbocode decoder as set forth in claim 93, wherein each decoder from saidplurality of decoders performs decoding substantially in parallel. 95.The turbo code decoder as set forth in claim 93, further comprising:index generation circuit for generating at least one index value, saidindex value determining a particular extrinsic value to be applied to adecoder from said plurality of decoders.
 96. The turbo code decoder asset forth in claim 93, wherein said at least one subsection of saidpseudo random interleaver includes a continuous set of addresses fromsaid pseudo random interleaver.
 97. The turbo code decoder as set forthin claim 95, wherein said index value corresponds to an address fromsaid at least one subsection divided by a size of said at least onsubsection.
 98. The turbo code decoder as set forth in claim 93, whereinsaid subsection of said pseudo random interleaver contain addresses, andaddresses from corresponding locations in said subsection have differentindex values.
 99. The turbo code decoder as set forth in claim 93,wherein said plurality of decoders further use receive samples forperforming decoding.
 100. The turbo code decoder as set forth in claim93, wherein said plurality of decoders performs soft-in-soft-outdecoding.
 101. The turbo code decoder as set forth in claim 93, whereinsaid extrinsic information is calculated during a previous decoding bysaid plurality of decoders.
 102. The turbo code decoder as set forth inclaim 93, wherein an address generated by said interleaver circuit isgenerated using a value calculated during a previous addresscalculation.
 103. A turbo code decoder for decoding a frame of encodeddata comprising: interleaver generation circuit for generating at leasta portion of a pseudo random interleaver, said portion having at least afirst address; index generation circuit for generating an index valuebased on said first address; and router circuit for routing extrinsicinformation based said index value.
 104. The turbo code decoder as setforth in claim 103, wherein said index value is different from otherindex values being processed at substantially the same time.
 105. Theturbo code decoder as set forth in claim 103, wherein said portion ofsaid interleaver is a continuous span of addresses in said interleaver.106. The turbo code decoder as set forth in claim 103, furthercomprising: decoder circuit for receiving routed extrinsic informationfrom said router circuit and for decoding a portion of said frame usingsaid routed extrinsic information.
 107. The turbo code decoder as setforth in claim 103, further comprising: first decoder circuit fordecoding a first section of said frame using extrinsic informationreceived from said router circuit; second router circuit for routingsecond extrinsic information based on a second index value; and seconddecoder for decoding a second section of said frame using extrinsicinformation received from said second router circuit.
 108. The turbocode decoder as set forth in claim 103, further comprising; secondinterleaver generation circuit for generating at least a second portionof said interleaver, said second portion having at least a secondaddress having a second index value, wherein said first address has afirst location within said first portion and said second address havinga second location within said second portion, and wherein said firstlocation and said second location are substantially the same and whereinsaid index value and said second index value are different.
 109. Theturbo code decoder as set forth in claim 108, wherein said secondportion of said interleaver is a continuous span of addresses in saidinterleaver.
 110. The turbo code decoder as set forth in claim 107,wherein said extrinsic information is generated during a previousdecoding of said frame by said first decoder circuit.
 111. The turbocode decoder as set forth in claim 107, wherein said first decodercircuit performs soft-in-soft-out decoding.
 112. A turbo code decoderfor decoding a frame of encoded data comprising: interleaver generationcircuit for generating at least a first portion of an interleaver, saidinterleaver being pseudo random, said first portion having at least afirst set of addresses; index generation circuit for generating a firstset of index values based on said first set of addresses; and routercircuit for routing a set of extrinsic information based said set ofindex values.
 113. The turbo code decoder of claim 112, wherein saidfirst set of addresses is a continuous section of addresses from saidinterleaver.
 114. The turbo code decoder of claim 112, furthercomprising: second interleaver generation circuit for generating asecond portion of said interleaver substantially simultaneous with saidinterleaver generation circuit; and second index generation circuit forgenerating a second set of index values based on said second portion ofsaid interleaver; wherein said first set of index values are differentfrom said second set of index values at a same location.
 115. The turbocode decoder of claim 114, wherein said first set of addresses is acontinuous section of addresses from said interleaver and said secondset of address is a continuous section of addresses from saidinterleaver.
 116. The turbo code decoder of claim 115, furthercomprising: second index generation circuit for generating a second setof index values based on a second portion of said interleaver, whereinsaid first set of index values are different from said second set ofindex values at a same location.
 117. The turbo code decoder circuit ofclaim 116, further comprising: first decoder circuit for decoding afirst portion of said frame; second decoder circuit for decoding asecond portion of said from substantially simultaneously with said firstdecoder.
 118. The turbo code decoder circuit of claim 112, wherein saidfirst set of index values are based on first set of addresses divided bya size of a subsection of said interleaver.
 119. The turbo code decodercircuit of claim 112, wherein said extrinsic information is generatedduring a previous decoding of said frame.
 120. A decoder circuit forperforming turbo code decoding on received estimates for a frame ofencoded data, said frame of encoded data being encoded using aninterleaver, said interleaver being pseudo random, said interleaverbeing comprising of a series of addresses in an order, each addresshaving a location within said interleaver, said interleaver furtherhaving interleaver subsections, each interleaver subsection being acontinuous set of addresses within said interleaver, said decodercircuit being comprised of: plurality of memory elements each forstoring a set of extrinsic values associated with a differentinterleaver subsection from said interleaver subsections; indexgeneration circuit for generating sets of index values based on sets ofaddresses, said sets of addresses containing one address from eachinterleaver subsection; and plurality of decoder circuits each forreceiving extrinsic information and for decoding a portion of saidframe, wherein said extrinsic information is routed to said plurality ofdecoders based on said set of index values.
 121. The decoder circuit asset forth in claim 120, wherein each address in a set of addresses fromsaid sets of addresses has a different index value.
 122. The decodercircuit as set forth in claim 120, wherein each address in a set ofaddress from said sets of addresses has a location within acorresponding interleaver subsection that is the same.
 123. The decodercircuit as set forth in claim 122, wherein said index value is a valueof said address divided by a size of said interleaver subsection. 124.The decoder circuit as set forth in claim 120, wherein said index valueis a value of said address divided by a size of said interleaversubsection.
 125. The decoder circuit as set forth in claim 125, whereinsaid extrinsic information is an estimate of said frame generated duringa previous decoding iterations.
 126. The decoder circuit as set forth inclaim 120, wherein said extrinsic information is a set of extrinsicvalues.
 127. A method for decoding a frame of encoded data comprisingthe steps of: decoding a first subsection of said frame of data; anddecoding a second subsection of said frame of data; wherein said firstsubsection is defined by a first set of addresses in an interleaver andsaid second subsection is defined by a second subsection of addresses insaid interleaver, and wherein an first address from said firstsubsection and a first address from a second subsection have differentindex values.
 128. The method as set forth in claim 127, wherein saidindex value is an address divided by a size of a subsection.
 129. Themethod as set forth in claim 127, wherein said first subsection includesa continuous section of addresses in said interleaver and said secondsubsection include a second continuous section of address in saidinterleaver.
 130. The method as set forth in claim 127, wherein saiddecoding of said first subsection and said decoding of said secondsubsection occur substantially simultaneously.
 131. The method as setforth in claims 129, wherein addresses with identical locations in saidfirst subsection and said second subsection have different index values.132. The method as set forth in claim 127, wherein an index value isequal to an address divided by a size of said subsection.
 133. Themethod as set forth in claim 127 wherein said first decoding step isperformed by the step of performing soft-in-soft-out decoding.
 134. Themethod as set forth in claim 133, wherein said second decoding step isperformed by the step of performing soft-in-soft-out decoding.
 135. Themethod as set forth in claim 127, wherein said first decoding step isperformed using extrinsic information selected based on first subsectionand said second decoding step is performed using extrinsic informationselected based on said second subsection.
 136. The method as set forthin claim 135, wherein said extrinsic information is calculated during aprevious decoding of said frame of encoded data.
 137. A method fordecoding a frame of encoded data comprising the steps of: repeatedlyreceiving sets of extrinsic values; and decoding multiple portions ofsaid frame simultaneously in response to said sets of extrinsic values,wherein said sets of extrinsic values are selected based sets ofaddresses, each address in a set of addresses having a unique indexvalue.
 138. The method as set forth in claim 137, wherein each portionof said frame is decoded using one value from a set of extrinsic valuesfrom said sets of extrinsic values.
 139. The method as set forth inclaim 137, wherein said index is equal to said address divided by asubsection size.
 140. The method as set forth in claim 137, furthercomprising the steps of: generating interleaver addresses for selectingone or more of said extrinsic values; and calculating index values basedon said addresses.
 141. The method as set forth in claim 140, whereinsaid index values are calculated by divided said addresses by a size ofa subsection.
 142. The method as set forth in claim 137, wherein saidset of addresses are selected from a corresponding set of interleaversubsections, each interleaver subsection being a different continuousportion of an interleaver used to encode said frame.
 143. The method asset forth in claim 150, wherein said sets of addresses are sets ofidentically located addresses within said sets of interleaversubsections.
 144. The method as set forth in claim 137, wherein saiddecoding step is further performed in response to a set of receivedestimates of said frame.
 145. The method as set forth in claim 137,wherein said extrinsic values are calculated during a previous decodingof said frame of encoded data.
 146. A turbo code decoder for decoding aframe of encoded data, said encoded data being encoded using a turbocode encoder having an interleaver, said interleaver being pseudorandom, said turbo code decoder comprising: first decoder for decoding afirst portion of said frame, wherein said first portion is less than allof said frame; second decoder for decoding a second portion of saidframe, wherein said second portion is less than all of said frame and isnot identical to said first portion; interleaver circuit for generatinga first set of addresses and a second set of addresses; index generationcircuit for generating a first set of index values base on said firstset of addresses and a second said of index values based on said secondset of addresses; first memory for storing a first subsection ofextrinsic information; second memory for storing a second subsection ofextrinsic information, wherein index values from said first set of indexvalues and said second set of index values are different when having thesame location.
 147. The turbo code decoder as set forth in claim 146,wherein index values in said first set of index values are calculated bydividing an address by a size of said first subsection.
 148. The turbocode decoder as set forth in claim 147, wherein index values in saidfirst set of index values are calculated by dividing an address by asize of said first subsection.
 149. The turbo code decoder as set forthin claim 146, wherein index values in said first set of index values arecalculated by dividing an address by a row size.
 150. The turbo codedecoder as set forth in claim 147, wherein index values in said firstset of index values are calculated by dividing an address by a row size.151. The turbo code decoder as set forth in claim 146, furthercomprising: first routing circuit for routing extrinsic values from saidfirst memory and said second memory based on said first set of indexvalues.
 152. The turbo code decoder as set forth in claim 146, furthercomprising: first routing circuit for routing extrinsic values from saidfirst memory and said second memory to said first decoder based on saidfirst set of index values.
 153. The turbo code decoder as set forth inclaim 146, further comprising: second routing circuit for routingextrinsic values from said first memory and said second memory to saidsecond decoder based on said first set of index values.
 154. The turbocode decoder as set forth in claim 146, wherein said decoder is asoft-in-soft-out decoder.
 155. The turbo code decoder as set forth inclaim 149, wherein said decoder is a soft-in-soft-out decoder.
 156. Theturbo code decoder as set forth in claim 152, wherein said decoder is asoft-in-soft-out decoder.
 157. The turbo code decoder as set forth inclaim 146, wherein said extrinsic information comprise estimates of saidencoded frame generated during a previous decoding.
 158. The turbo codedecoder as set forth in claim 146, wherein received estimates of saidframe are used by said first decoder.
 159. A decoder circuit forperforming turbo code decoding on received estimates for a frame ofencoded data, said frame of encoded data being encoded using aninterleaver, said interleaver being pseudo random, said interleaverbeing comprising of a series of addresses in an order, each addresshaving a location within said interleaver, said interleaver furtherhaving interleaver subsections, each interleaver subsection being acontinuous set of addresses within said interleaver, said decodercircuit being comprised of: means for storing sets of extrinsic values,each set of extrinsic values associated with a different interleaversubsection from said interleaver subsections; means for generating setsof index values based on sets of addresses, said sets of addressescontaining one address from each interleaver subsection; means forreceiving different sets of extrinsic information and for decodingportions of said frame simultaneous, wherein said sets of extrinsicinformation is routed to said plurality of decoders based on said set ofindex values.
 160. The decoder circuit as set forth in claim 159,wherein each address in a set of addresses from said sets of addresseshas a different index value.
 161. The decoder circuit as set forth inclaim 160, wherein each address in a set of address from said sets ofaddresses has a location within a corresponding interleaver subsectionthat is the same.
 162. The decoder circuit as set forth in claim 159,wherein said index value is a value of said address divided by a size ofsaid interleaver subsection.
 163. The decoder circuit as set forth inclaim 159, wherein said index value is a value of said address dividedby a size of said interleaver subsection.
 164. The decoder circuit asset forth in claim 159, wherein said extrinsic information is anestimate of said frame generated during a previous decoding iterations.165. The decoder circuit as set forth in claim 159, wherein saidextrinsic information is a set of extrinsic values.
 166. An apparatusfor decoding a frame of encoded data comprising: means for repeatedlyreceiving sets of extrinsic values; means for decoding multiple portionsof said frame simultaneously in response to said sets of extrinsicvalues, wherein said sets of extrinsic values are selected based sets ofaddresses, each address in a set of addresses having a unique indexvalue.
 167. The apparatus as set forth in claim 166, wherein eachportion of said frame is decoded using one value from a set of extrinsicvalues from said sets of extrinsic values.
 168. The apparatus as setforth in claim 166, wherein said index is equal to said address dividedby a subsection size.
 169. The apparatus as set forth in claim 166,further comprising: means for generating interleaver addresses forselecting one or more of said extrinsic values.
 170. The apparatus asset forth in claim 168, further comprising the step of: means forcalculating index values based on said addresses.
 171. The apparatus asset forth in claim 170, wherein said index values are calculated bydivided said addresses by a size of a subsection.
 172. The apparatus asset forth in claim 166, wherein said set of addresses are selected froma corresponding set of interleaver subsections, each interleaversubsection being a different continuous portion of an interleaver usedto encode said frame.
 173. The apparatus as set forth in claim 172,wherein said sets of addresses are sets of identically located addresseswithin said sets of interleaver subsections.
 174. The apparatus as setforth in claim 166, wherein said decoding step is further performed inresponse to a set of received estimates of said frame.
 175. Theapparatus as set forth in claim 166, wherein said extrinsic values arecalculated during a previous decoding of said frame of encoded data.